LC470EUF
Product Specification
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS
-
LVDS
+
V CM
VIN _ MAX V IN _ MIN
# VCM = {(LVDS +) + ( LVDS -)}/2
0V
Description
LVDS Common mode Voltage
LVDS Input Voltage Range
Change in common mode Voltage
2) AC Specification
Symbol
VCM
Min
1.0
0.7
Max
1.5
Unit
V
Note
-
-
-
VIN
1.8
V
ΔVCM
250
mV
Tclk
LVDS Clock
LVDS Data
A
(Fclk = 1/Tclk
)
t
SKEW
t
SKEW
A
Tclk
LVDS 1’st Clock
80%
20%
LVDS 2nd / 3rd / 4th Clock
tRF
tSKEW_min tSKEW_max
Description
Symbol
VTH
Min
100
-300
-
Max
300
Unit
mV
Note
High Threshold
Low Threshold
LVDS Differential Voltage
3
VTL
-100
mV
ps
ps
ps
ps
LVDS Clock to Data Skew
tSKEW
tRF
|(0.25*Tclk)/7|
|(0.3*Tclk)/7|
-
-
2
-
LVDS Clock/DATA Rising/Falling time
Effective time of LVDS
260
teff
|±360|
LVDS Clock to Clock Skew (Even to Odd)
tSKEW_EO
-
|1/7* Tclk|
-
Note 1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If tRF isn’t enough, teff should be meet the range.
3. LVDS Differential Voltage is defined within teff
13 /40
Ver. 1.5
LG [ LG SEMICON CO.,LTD. ]
