LG Semicon
GM72V66841CT/CLT
Clock Suspend (Active Power Down) Mode
0
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
4
CLK
CKE
CS
RAS
CAS
WE
A12/A13(BS)
R:a
C:a
R:b
a
C:b
Address
DQM ,
DQMU/DQML
a+1
a+2
a+3
b
b+1 b+2 b+3
DQ(output)
DQ(input)
High-Z
Bank3 Bank0
Read Precharge
Earliest Bank3
Precharge
Bank0 Active Clock
Active Suspend Start
Bank0
Read
Bank3 Read Suspend
Active
Start
Read Suspend End
Active Clock Suspend End
Read Cycle , RAS-CAS Delay=2
CAS Latency=2 , Burst Length=4
= VIH or VIL
CKE
CS
RAS
CAS
WE
A12/A13(BS)
Address
R:a
C:a R:b
C:b
DQM ,
DQMU/DQML
High-Z
DQ(output)
DQ(input)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
Bank0 Active Clock
Active Suspend Start
Bank0 Bank3 Write Suspend
Write Active Start
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
Active Clock Suspend End
Write Suspend End
Write Cycle , RAS-CAS Delay=2
CAS Latency=2 , Burst Length=4
= VIH or VIL
53
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