LG Semicon
GM72V66841CT/CLT
Read / Single Write Cycle
0
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
4
CLK
CKE
CS
VIH
RAS
CAS
WE
A12/A13
.
R:a
C:a
R:b
C:a C:a
Address
DQM ,
DQMU/DQML
a
DQ(input)
DQ(output)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank0 Bank3
Bank0
Active
Bank0
Read
Bank3
Active
Bank0 Bank0
Write Read
Precharge Precharge
CKE
CS
VIH
RAS
CAS
WE
A12/A13
R:a
C:a
R:b
C:a
a
C:b C:c
Address
DQM ,
DQMU/DQML
DQ(input)
b
c
a
a+1
a+3
DQ(output)
Bank0
Active
Bank0
Read
Bank3
Active
Bank0
Write
Bank0 Bank0
Write Write
Bank0
Precharge
Read/Single Write Cycle
RAS-CAS Delay=3
CAS Latency=3
Burst Length=4
= VIH or VIL
48