Revision History
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Date
Version
Section
Change Summary
September 2005
02.0
Architecture
sysIO section has been updated.
Recommended Operating Conditions has been updated with V
DC & Switching
Characteristics
.
CCPLL
DC Electrical Characteristics table has been updated
Removed 5V Tolerant Input Buffer section.
Register-to-Register performance table has been updated (rev. G 0.28).
LatticeECP/EC External Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Internal Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28).
sysCLOCK PLL timing table has been updated (rev. G 0.28)
LatticeECP/EC sysCONFIG Port Timing specification table has been
updated (rev. G 0.28).
Master Clock table has been updated (rev. G 0.28).
JTAG Port Timing specification table has been updated (rev. G 0.28).
Pinout Information
Signal Description table has been updated with V
.
CCPLL
November 2005
02.1
DC & Switching
Characteristics
Pin-to-Pin Performance table has been updated (G 0.30)
- 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX
Register-to-Register Performance (G 0.30) - No timing number
changes.
External Switching Characteristics (G 0.30) - No timing number
changes.
Internal Switching Characteristics (G 0.30)
-t
t
, t
t
t
, t
numbers
SUP_DSP, HP_DSP SUO_DSP, HO_DSP, COI_DSP COD_DSP
have been updated.
Family Timing Adders (G 0.30) - No timing number changes.
sysCLOCK PLL Timing (G 0.30) - No timing number changes.
sysCONFIG Port Timing Specifications (G 0.30) - No timing number
changes.
Master Clock (G 0.30) - No timing number changes.
JTAG Port Timing Specification (G 0.30) - No timing number changes.
Ordering Information Added 208-PQFP lead-free part numbers.
March 2006
02.2
DC & Switching
Characteristics
Added footnote 3. to V
tions table.
in the Recommended Operating Condi-
CCAUX
January 2007
February 2007
02.3
02.4
Architecture
Architecture
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated Maximum Number of Elements in a Block table - MAC value
for x9 changed to 2.
May 2007
02.5
02.6
Architecture
Updated text in Ripple Mode section.
Added JTAG Port Waveforms diagram.
November 2007
DC & Switching
Characteristics
Updated t
timing information in the sysCLOCK PLL Timing table.
RST
Pinout Information
Added Thermal Management text section.
Updated title list.
Supplemental
Information
February 2008
02.7
DC & Switching
Characteristics
Read/Write Mode (Normal) and Read/Write Mode with Input and Output
Registers waveforms in the EBR Memory Timing Diagrams section
have been updated.
7-3
LATTICE [ LATTICE SEMICONDUCTOR ]
