Revision History
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Date
Version
Section
Architecture
Change Summary
December 2004
01.4
Updated Hot Socketing Recommended Power Up Sequence section.
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Pin Information
Pinout Information
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Power Supply
and NC Connections
Added LFEC1 and LFEC3 100 TQFP Pinout
Added LFEC1 and LFEC3 144 TQFP Pinout
Added LFEC1, LFEC3 and LFECP/EC10 208 PQFP Pinout
Added LFEC3, LFECP/EC10 and LFECP/EC15 256 fpBGA Pinout
Added LFECP/EC10 and LFECP/EC15 484 fpBGA Pinout
Ordering Information Added Lead-Free Package Designators
Added Lead-Free Ordering Part Numbers
Supplemental
Information
Updated list of technical notes.
April 2005
01.5
Architecture
EBR memory support section has been updated with clarification.
Updated sysIO buffer pair section.
DC & Switching
Characteristics
Hot Socketing Specification has been updated.
DC Electrical Characteristics table (I , I ) has been updated.
IL IH
Supply Current (Standby) table has been updated.
Initialization Supply Current table has been updated.
External Switching Characteristics section has been updated.
Removed t
spec. from PLL Parameter table.
RSTW
t
specifications have been updated.
RST
sysCONFIG Port Timing Specifications (t
been updated.
t
t
) have
BSCL, IODISS, PRGMRJ
Pinout Information
Added LFECP/EC33 Pinout Information
Pin Information Summary table has been updated.
Power Supply and NC Connection table has been updated.
484-fpBGA logic connection has been updated (Ball # J6, J17, P6 and
P17 for ECP/EC33 are now called VCCPLL).
672-fpBGA logic connection has been updated (Ball # K19, L8, U19, U8
for ECP/EC33 are now called VCCPLL).
May 2005
01.6
Introduction
Architecture
ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K
and 54 respectively.
Table 2-10 has been updated (ECP/EC33 EBR SRAM Bits and Blocks
have been updated to 498K and 54 respectively.)
Recommended Power Up Sequence section has been removed.
Supply Current (Standby) table has been updated.
DC & Switching
Characteristics
Initialization Supply Current table has been updated.
Vos test condition has been updated to (VOP+VOM)/2.
Register-to-Register performance table has been updated (rev. G 0.27).
External switching characteristics have been updated (rev. G 0.27).
Internal timing parameters have been updated (rev. G 0.27).
Timing adders have been updated (rev. G 0.27).
sysCONFIG port timing specifications have been updated.
Pin Information Summary table has been updated.
Pinout Information
Power Supply and NC Connection table has been updated.
Ordering Information OPN list has been updated.
7-2
LATTICE [ LATTICE SEMICONDUCTOR ]
