Specifications
ispLSI 2064V
ispLSI 2064V Timing Model
I/O Cell
GRP
Feedback
Ded. In
Comb 4 PT Bypass #23
GLB
ORP
I/O Cell
#21
I/O Delay
#20
GRP
#22
20 PT
XOR Delays
#25, 26, 27
Reset
#45
D
GLB Reg
Delay
Q
#29, 30,
31, 32
RST
ORP
Delay
#36
Y0,1,2
GOE 0,1
#43, 44
#42
N
EW
Control RE
PTs
OE
#33, 34, CK
35
D
#40, 41
0491/2064
t
su
4.6 ns
0.7 ns
t
co
10.1 ns
pL
Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.
Table 2-0042/2064V
U
SE
is
SI
2
=
=
=
=
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)
06
4V
t
h
=
=
=
=
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)
E
=
=
=
=
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)
FO
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
7
R
1
ES
IG
N
I/O Pin
(Input)
#24
#28
#37
S
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#38,
39
I/O Pin
(Output)
LATTICE [ LATTICE SEMICONDUCTOR ]
