Specifications
ispLSI 2064V
Power Consumption
Power consumption in the ispLSI 2064V device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
120
ispLSI 2064V
110
100
Figure 3 shows the relationship between power and
operating speed.
I
CC (mA)
80
70
0
25
50
f
max (MHz)
ICC can be estimated for the ispLSI 2064V using the following equation:
ICC(mA) = 10 + (# of PTs * 0.556) + (# of nets * Max freq * 0.0053)
SI
2
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
06
4V
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
E
FO
R
Notes: Configuration of Four 16-bit Counters
Typical Current at 3.3V, 25° C
N
EW
75
100
D
0127/2064
90
When Lattice 3.3-Volt 2000V devices are used in mixed
5V/3.3V applications, some consideration needs to be
given to the power-up sequence. When the I/O pins on
the 3.3V ispLSI devices are driven directly by 5V devices,
a low impedance path can exist on the 3.3V device
between its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
flow from the 5V device into the 3.3V ispLSI device. The
maximum current occurs when the signals on the I/O pins
are driven high by the 5V devices. If a large enough
current flows through the 3.3V I/O pins, latch-up can
occur and permanent device damage may result.
pL
Power-up Considerations
SE
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device oper-
ating Vcc range of 3.0V to 3.6V.
The recommended power-up options are as follows:
Option 1: Ensure that the 3.3V supply is powered-up and
stable before the 5V supply is powered up.
Option 2: Ensure that the 5V device outputs are driven to
a high impedance or logic low state during power-up.
U
is
8
ES
IG
N
S
LATTICE [ LATTICE SEMICONDUCTOR ]
