Specifications
ispLSI 2064V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
DESCRIPTION
1
-100
–
–
3
1
tsu2 + tco1
-80
–
–
80.0
64.5
100
7.0
–
10.0
15.0
–
–
–
–
–
–
-60
15.0
20.0
–
–
–
–
–
–
–
16.0
–
18.0
18.0
12.0
12.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
12.0
–
–
–
–
5.0
–
–
–
–
6.3
UNITS
ns
ns
MHz
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Clock Frequency with External Feedback
(
102
61.7
51.3
71.4
9.0
–
0.0
–
0.0
–
8.0
–
–
–
–
7.0
7.0
)
N
8.5
9.5
83.3
125
5.5
–
0.0
7.0
–
0.0
–
–
–
–
–
4.0
4.0
5.0
ES
IG
6.5
–
–
–
14.0
–
15.0
15.0
10.0
10.0
–
–
11.0
–
–
7.5
–
–
–
–
0.0
9.0
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
D
0.0
7.0
5.0
5.0
N
EW
12.0
13.0
13.0
7.5
7.5
–
–
R
FO
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
E
U
SE
is
pL
SI
2
06
4V
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030/2064V
5
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
LATTICE [ LATTICE SEMICONDUCTOR ]
