Specifications ispGDX Family
Pin Configuration: ispGDX80A
ispGDX80A 100-Pin TQFP Pinout Diagram
Data
Control
Control
Data
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
GND
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
VCC
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O B0
I/O B1
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O D1
I/O D0
I/O C19
I/O C18
I/O C17
I/O C16
I/O C15
GND
I/O C14
I/O C13
I/O C12
I/O C11
I/O C10
VCC
I/O C9
I/O C8
I/O C7
I/O C6
I/O C5
GND
I/O C4
I/O C3
I/O C2
I/O C1
I/O C0
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
—
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
CLK
9
MUXsel1
OE
CLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MUXsel2
MUXsel1
—
ispGDX80A
Top View
OE
CLK
MUXsel2
MUXsel1
OE
—
CLK
MUXsel2
MUXsel1
OE
OE
MUXsel1
MUXsel2
CLK
OE
CLK
1. Pins have dual function capability.
24
LATTICE [ LATTICE SEMICONDUCTOR ]
