Specifications
GAL26CLV12
f
max Descriptions
CLK
LOGIC
ARRAY
REGISTER
CLK
LOGIC
ARRAY
t
su
t
co
REGISTER
f
max with External Feedback 1/(
t
su+
t
co)
Note: fmax
with external feedback is calculated from measured
tsu
and
tco.
CLK
t
cf
t
pd
LOGIC
ARRAY
f
max with Internal Feedback 1/(
t
su+
t
cf)
REGISTER
t
su +
t
h
f
max with No Feedback
Note: fmax
with no feedback may be less than 1/(twh +
twl).
This
is to allow for a clock duty cycle of other than 50%.
Note: tcf
is a calculated value, derived by subtracting
tsu
from
the period of fmax w/internal feedback (tcf = 1/fmax -
tsu).
The
value of
tcf
is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to
tcf
+
tpd.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
Output Load Conditions (see figure)
Test Condition
A
B
C
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
R
1
50Ω
50Ω
50Ω
50Ω
50Ω
C
L
35pF
35pF
35pF
35pF
35pF
GND to 3.0V
1.5ns 10% – 90%
1.5V
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
Z
0
= 50Ω, C
L
= 35pF*
TEST POINT
R
1
+1.45V
*C
L
includes test fixture and probe capacitance.
9
LATTICE [ LATTICE SEMICONDUCTOR ]
