Specifications GAL26CLV12
Electronic Signature
Output Register Preload
An electronic signature (ES) is provided in every GAL26CLV12D When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogrammable memory that can transitions must be verified in the design, not just those required
contain user-defined data. Some uses include user ID codes, in the normal machine operations. This is because certain events
revision numbers, or inventory control. The signature data is al- may occur during system operation that throw the logic into an il-
ways available to the user independent of the state of the security legal state (power-up, line voltage glitches, brown-outs, etc.). To
cell.
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
Security Cell
Asecurity cell is provided in every GAL26CLV12D device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
The GAL26CLV12D device includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test vec-
tors perform output register preload automatically.
Input Buffers
Latch-Up Protection
GAL26CLV12D devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
GAL26CLV12D devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of suf-
ficient magnitude to prevent input undershoots from causing the
circuitry to latch.
The input and I/O pins on the GAL26CLV12D also have built-in ac-
tive pull-ups. As a result, floating inputs will float to a TTL high (logic
1). However, Lattice Semiconductor recommends that all unused
Device Programming
GAL devices are programmed using a Lattice Semiconductor- inputs and tri-stated I/O pins be connected to an adjacent active
approved Logic Programmer, available from a number of manu- input, Vcc, or ground. Doing so will tend to improve noise immu-
facturers (see the the GAL Development Tools section). Complete nity and reduce Icc for the device. (See equivalent input and I/O
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
schematics on the following page.)
part of the programming cycle.
Typical Input Pull-up Characteristic
0
-10
-20
-30
-40
-50
-60
-70
-80
Input Voltage (V)
10
LATTICE [ LATTICE SEMICONDUCTOR ]
