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GAL22V10B-15LJ 参数 Datasheet PDF下载

GAL22V10B-15LJ图片预览
型号: GAL22V10B-15LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 29 页 / 387 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL22V10D  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-4  
COM  
-5  
COM/IND  
-7  
TEST  
DESCRIPTION  
Input or I/O to Combinatorial Output  
PARAM  
COND.1  
UNITS  
MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
1
4
1
5
1
7.5  
4.5  
3
ns  
ns  
ns  
ns  
Clock to Output Delay  
1
3.5  
2.5  
1
4
1
Clock to Feedback Delay  
2.5  
3
3
4.5  
Setup Time, Input or Fdbk before Clk↑  
Hold Time, Input or Fdbk after Clk↑  
0
0
0
ns  
A
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
167  
142.8  
111  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
200  
250  
166  
200  
133  
166  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
B
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
Input or I/O to Output Enabled  
2
2
1
5
2.5  
2.5  
1
6
3
3
1
ns  
ns  
ns  
ten  
7.5  
tdis  
tar  
C
A
Input or I/O to Output Disabled  
1
1
5
1
1
5.5  
5.5  
1
1
7.5  
9
ns  
ns  
Input or I/O to Asynch. Reset of Reg.  
4.5  
tarw  
tarr  
Asynch. Reset Pulse Duration  
4.5  
3
4.5  
4
7
5
5
ns  
ns  
ns  
Asynch. Reset to ClkRecovery Time  
Synch. Preset to ClkRecovery Time  
tspr  
3
4
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Description section.  
3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these  
parameters.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
CI/O  
pF  
*Characterized but not 100% tested.  
7