Specifications GAL22LV10
ELECTRONIC SIGNATURE
OUTPUT REGISTER PRELOAD
An electronic signature (ES) is provided in every GAL22LV10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22LV10 and a GAL22V10-UES (UES = User Electronic Sig-
nature) or GAL22V10-ES. This allows users to maintain compat-
ibility with existing 22V10 designs, while still having the option to
use the GAL device's extra feature.
The GAL22LV10 device includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
INPUT BUFFERS
The JEDEC map for the GAL22LV10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22LV10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
GAL22LV10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar
TTL devices.
The input and I/O pins on the GAL22LV10D also have built-in ac-
tive pull-ups. As a result, floating inputs will float to a TTL high
(logic 1). However, Lattice Semiconductor recommends that all
unused inputs and tri-stated I/O pins be connected to an adjacent
active input, Vcc, or ground. Doing so will tend to improve noise
immunity and reduce Icc for the device. (See equivalent input and
I/O schematics on the following page.)
SECURITY CELL
A security cell is provided in every GAL22LV10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
Typical Input Pull-up Characteristic
0
-10
-20
-30
-40
-50
-60
-70
-80
LATCH-UP PROTECTION
GAL22LV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.
Input Voltage (V)
13
LATTICE [ LATTICE SEMICONDUCTOR ]
