Specifications GAL20RA10
Electronic Signature
Device Programming
An electronic signature word is provided in every GAL20RA10 GAL devices are programmed using a Lattice Semiconductor-
device. It contains 64 bits of reprogrammable memory that con- approved Logic Programmer, available from a number of manu-
tains user defined data. Some uses include user ID codes, revi- facturers (see the the GAL Development Tools section). Complete
sion numbers, pattern identification or inventory control codes. The programming of the device takes only a few seconds. Erasing of
signature data is always available to the user independent of the the device is transparent to the user, and is done automatically as
state of the security cell.
part of the programming cycle.
NOTE: The electronic signature bits if programmed to any value
other then zero(0) will alter the checksum of the device.
Input Buffers
GAL20RA10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
Security Cell
A security cell is provided in every GAL20RA10 device as a deter- bipolar devices.
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device GAL20RA10 input buffers have active pull-ups within their input
pattern information. This cell can be only be reset by reprogram- structure. As a result, unused inputs and I/Os will float to a TTL
ming the device. The original pattern can never be examined once “high” (logical “1”). Lattice Semiconductor recommends that all un-
this cell is programmed. The Electronic Signature is always avail- used inputs and tri-stated I/O pins be connected to another active
able regardless of the security cell state.
input, Vcc, or GND. Doing this will tend to improve noise immu-
nity and reduce Icc for the device.
Latch-Up Protection
Typical Input Pull-up Characteristic
GAL20RA10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
0
- 2 0
- 4 0
- 6 0
0
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
Input Voltage (Volts)
10
LATTICE [ LATTICE SEMICONDUCTOR ]
