Specifications GAL20LV8
fmax Descriptions
C L K
LOGIC
ARR AY
REGISTER
CLK
LOGIC
ARRAY
t
s u
tc o
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
t
cf
pd
CLK
t
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
REGISTER
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Output Load Conditions (see figure)
Input Pulse Levels
GND to 3.0V
1.5ns 10% – 90%
1.5V
Test Condition
R1
CL
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
A
50Ω
50Ω
50Ω
50Ω
50Ω
35pF
35pF
35pF
35pF
35pF
B
High Z to Active High at 1.9V
1.5V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
C
See Figure
+1.45V
TEST POINT
R1
FROM OUTPUT (O/Q)
UNDER TEST
Z
0
= 50Ω, C = 35pF*
L
*CL includes test fixture and probe capacitance.
13
LATTICE [ LATTICE SEMICONDUCTOR ]
