Specifications GAL20LV8
Power-Up Reset
Vcc (min.)
Vcc
t
su
t
wl
CLK
t
pr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
provide a valid power-up reset of the device. First, the VCC rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will re-
set within a maximum of tpr time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum pulse
width requirements.
Circuitry within the GAL20LV8D provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Active Pull-up
Circuit
Active Pull-up
Circuit
Vcc
Tri-State
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Control
PIN
Data
Output
PIN
ESD
Protection
Circuit
Feedback
Typ. Vref = Vcc
Typ. Vref = Vcc
(To Input Buffer)
Typical Input
Typical Output
15
LATTICE [ LATTICE SEMICONDUCTOR ]
