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GAL20XV10B-15LJ 参数 Datasheet PDF下载

GAL20XV10B-15LJ图片预览
型号: GAL20XV10B-15LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高速E2CMOS PLD通用阵列逻辑 [High-Speed E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 14 页 / 235 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL20XV10
Input Mode
OE
D
Q
Q
XOR Registered Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 0.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- Pin 13(16) can be OE and/or Input.
CLK
D
XOR
Q
Q
Registered Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- OE controlled by product term.
CLK
OE
XOR Combinatorial Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 1.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 13(16) can be OE and/or Input.
XOR
Combinatorial Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- OE controlled by product term.
4