Specifications GAL20V8
fmax Descriptions
CL K
LOGIC
ARR AY
REGI STER
CLK
LOGIC
ARRAY
t
s u
t
c o
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
CLK
t
cf
pd
t
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
REGISTER
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
+5V
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
2 – 3ns 10% – 90%
1.5ns 10% – 90%
1.5V
R
1
GAL20V8B
GAL20V8C
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
C L*
R
2
See Figure
3-state levels are measured 0.5V from steady-state active
level.
*CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
GAL20V8B Output Load Conditions (see figure)
GAL20V8C Output Load Conditions (see figure)
Test Condition
R1
R2
CL
Test Condition
R1
R2
CL
A
200Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
A
200Ω
∞
200Ω
200Ω
200Ω
200Ω
200Ω
50pF
50pF
50pF
5pF
B
Active High
Active Low
Active High
Active Low
B
Active High
Active Low
Active High
Active Low
200Ω
∞
200Ω
∞
C
C
200Ω
5pF
200Ω
5pF
16
LATTICE [ LATTICE SEMICONDUCTOR ]
