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GAL18V10B-20LJ 参数 Datasheet PDF下载

GAL18V10B-20LJ图片预览
型号: GAL18V10B-20LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 16 页 / 267 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL18V10B  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
COM  
-10  
COM  
-15  
COM  
-20  
-7  
TEST  
COND.1  
DESCRIPTION  
PARAM.  
UNITS  
MIN. MAX.  
MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Comb. Output  
Clock to Output Delay  
7.5  
5.5  
3.5  
6
10  
7
8
15  
10  
7
12  
20  
12  
10  
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
3.5  
Setup Time, Input or Fdbk before Clk↑  
Hold Time, Input or Fdbk after Clk↑  
5.5  
0
0
0
0
ns  
A
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
90.9  
76.9  
55.5  
41.6  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
111  
111  
105  
105  
66.7  
66.7  
45.4  
62.5  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
B
Clock Pulse Duration, High  
4
4
8
4
4
10  
9
6
15  
15  
20  
8
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Pulse Duration, Low  
6
8
ten  
tdis  
tar  
Input or I/O to Output Enabled  
Input or I/O to Output Disabled  
Input or I/O to Asynch. Reset of Reg.  
Asynch. Reset Pulse Duration  
Asynch. Reset to ClkRecovery Time  
Synch. Preset to ClkRecovery Time  
8
8
10  
10  
10  
15  
15  
12  
C
8
A
13  
13  
tarw  
tarr  
tspr  
8
8
10  
10  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Description section.  
3) Refer to fmax Description section.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
pF  
pF  
CI/O  
*Characterized but not 100% tested.  
7
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