Specifications GAL18V10
GAL18V10 Logic Diagram/JEDEC Fuse Map
DIP and PLCC Package Pinouts
1
0
4
8
12
16
20
24
28
32
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0000
0036
.
.
.
8
OLMC
19
S0
0324
3456
S1
3457
0360
.
.
.
8
OLMC
18
S0
0648
3458
S1
3459
2
3
4
0684
.
8
.
.
OLMC
17
SO
0972
3460
S1
3461
1008
.
.
.
8
OLMC
16
S0
1296
3462
S1
3463
1332
.
.
10
OLMC
.
.
15
S0
3464
S1
3465
1692
5
6
1728
.
10
.
.
.
OLMC
14
S0
3466
S1
3467
2088
2124
.
.
.
8
OLMC
13
S0
2412
3468
S1
3469
7
8
2448
.
8
.
.
OLMC
12
S0
2736
3470
S1
3471
2772
.
.
.
8
OLMC
11
S0
3060
3472
S1
3473
3096
.
.
.
8
OLMC
9
S0
3384
3474
S1
3475
3420
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
Electronic Signature
... 3538, 3539
3476, 3477 ...
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M
S
B
L
S
B
5
LATTICE [ LATTICE SEMICONDUCTOR ]
