Specifications GAL16LV8
GAL16LV8D: Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5ns 10% – 90%
1.5V
+1.45V
1.5V
See Figure
TEST POINT
R1
GAL16LV8D Output Load Conditions (see figure)
FROM OUTPUT (O/Q)
UNDER TEST
Test Condition
R1
CL
Z0 = 50Ω, CL = 35pF*
A
50Ω
50Ω
50Ω
50Ω
50Ω
35pF
35pF
35pF
35pF
35pF
B
High Z to Active High at 1.9V
*CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
C
GAL16LV8C: Switching Test Conditions
+3.3V
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5ns 10% – 90%
1.5V
R1
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
GAL16LV8C Output Load Conditions (see figure)
C L*
R2
Test Condition
R1
R2
CL
A
B
316Ω
316Ω
316Ω
316Ω
316Ω
348Ω
348Ω
348Ω
348Ω
348Ω
35pF
35pF
35pF
5pF
Active High
Active Low
Active High
Active Low
C
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
5pF
16
LATTICE [ LATTICE SEMICONDUCTOR ]
