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GAL16LV8D-3LJ 参数 Datasheet PDF下载

GAL16LV8D-3LJ图片预览
型号: GAL16LV8D-3LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 低压E2CMOS PLD通用阵列逻辑 [Low Voltage E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 22 页 / 337 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16LV8  
fmax Descriptions  
C L K  
CLK  
LOGIC  
ARR AY  
REGISTER  
LOGIC  
ARRAY  
REGISTER  
t
s u  
tc o  
fmax with External Feedback 1/(tsu+tco)  
Note: fmax with external feedback is calculated from measured  
tsu and tco.  
t
cf  
pd  
CLK  
t
fmax with Internal Feedback 1/(tsu+tcf)  
LOGIC  
REGISTER  
ARRAY  
Note: tcf is a calculated value, derived by subtracting tsu from  
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The  
value of tcf is used primarily when calculating the delay from  
clocking a register to a combinatorial output (through registered  
feedback), as shown above. For example, the timing from clock  
to a combinatorial output is equal to tcf + tpd.  
t
su + th  
fmax with No Feedback  
Note: fmax with no feedback may be less than 1/(twh + twl). This  
is to allow for a clock duty cycle of other than 50%.  
15  
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