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GAL16VP8B-15LP 参数 Datasheet PDF下载

GAL16VP8B-15LP图片预览
型号: GAL16VP8B-15LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高速E2CMOS PLD通用阵列逻辑 [High-Speed E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 17 页 / 214 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16VP8  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-15  
COM  
-25  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX.  
MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Combinational Output  
3
2
15  
10  
4.5  
3
2
25  
15  
10  
ns  
ns  
ns  
ns  
Clock to Output Delay  
Clock to Feedback Delay  
8
10  
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
0
0
ns  
A
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
55.5  
40  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
80  
80  
50  
50  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
B
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
Input or I/O to Output Enabled  
OE to Output Enabled  
6
15  
12  
15  
12  
10  
10  
20  
15  
20  
15  
ns  
ns  
ns  
ns  
ns  
ns  
6
ten  
B
tdis  
C
Input or I/O to Output Disabled  
OE to Output Disabled  
C
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.  
3) Refer to fmax Specification section.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
10  
15  
CI/O  
pF  
*Characterized but not 100% tested.  
11  
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