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GAL16V8D-25LP 参数 Datasheet PDF下载

GAL16V8D-25LP图片预览
型号: GAL16V8D-25LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 22 页 / 315 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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SpecificationsGAL16V8D
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM / IND COM / IND  
IND  
-20  
COM / IND  
-25  
-10  
-15  
TEST  
COND1.  
DESCRIPTION  
PARAM.  
UNITS  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Comb. Output  
Clock to Output Delay  
3
2
10  
7
3
2
15  
10  
8
3
2
20  
11  
9
3
2
25  
12  
10  
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
7.5  
6
12  
13  
15  
Setup Time, Input or Fdbk before Clk↑  
Hold Time, Input or Fdbk after Clk↑  
A
0
0
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
66.7  
45.5  
41.6  
37  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
71.4  
83.3  
50  
45.4  
50  
40  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
62.5  
41.6  
twh  
twl  
ten  
t
B
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
Input or I/O to Output Enabled  
OE to Output Enabled  
6
6
1
1
1
1
10  
10  
10  
10  
8
15  
15  
15  
15  
10  
10  
18  
18  
18  
18  
12  
12  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
8
B
tdis  
t
C
Input or I/O to Output Disabled  
OE to Output Disabled  
C
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section. Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
pF  
pF  
CI/O  
*Characterized but not 100% tested.  
12