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GAL16V8D-25LP 参数 Datasheet PDF下载

GAL16V8D-25LP图片预览
型号: GAL16V8D-25LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 22 页 / 315 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16V8D  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-5  
COM / IND  
-7  
COM  
-3  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
A
A
Input or I/O to Comb. Output  
Clock to Output Delay  
1
1
3.5  
3
1
1
5
4
3
1
1
7.5  
5
ns  
ns  
ns  
Clock to Feedback Delay  
2.5  
3
tsu  
th  
A
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
2.5  
0
3
0
5
0
ns  
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
182  
142.8 — 100  
MHz  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
200  
250  
166  
166  
125  
125  
MHz  
MHz  
fmax3  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
24  
24  
34  
34  
4
4
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
4.5  
4.5  
1
1
6
6
1
1
9
6
ns  
ns  
OE to Output Enabled  
tdis  
C
C
Input or I/O to Output Disabled  
4.5  
4.5  
1
1
5
5
1
1
9
6
ns  
ns  
OE to Output Disabled  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section. Characterized but not 100% tested.  
4) Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
CI/O  
pF  
*Characterized but not 100% tested.  
11