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GAL16V8D-25LJ 参数 Datasheet PDF下载

GAL16V8D-25LJ图片预览
型号: GAL16V8D-25LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 22 页 / 315 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16V8  
Complex Mode  
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the  
I/O functions. Registered mode.  
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product  
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and  
each macrocell.  
11 are always available as data inputs into the AND array.  
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses  
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.  
two outer most macrocells (pins 12 & 19) do not have input capa-  
Combinatorial I/O Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 13 through Pin 18 are configured to this function.  
Combinatorial Output Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 12 and Pin 19 are configured to this function.  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
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