Specifications GAL16V8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
PAL Architectures
Emulated by GAL16V8
GAL16V8
Global OLMC Mode
16R8
16R6
16R4
16RP8
16RP6
16RP4
Registered
Registered
Registered
Registered
Registered
Registered
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ-
ual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
16L8
16H8
16P8
Complex
Complex
Complex
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes as clock and output enable, respectively. These pins cannot be con-
as different device types. These device types are listed in the table figured as dedicated inputs in the registered mode.
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output In complex mode pin 1 and pin 11 become dedicated inputs and
enable (OE) usage. Register usage on the device forces the soft- use the feedback paths of pin 19 and pin 12 respectively. Because
ware to choose the registered mode. All combinatorial outputs with of this feedback path usage, pin 19 and pin 12 do not have the
OE controlled by the product term will force the software to choose feedback option in this mode.
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control. In simple mode all feedback paths of the output pins are routed
The different device types listed in the table can be used to override via the adjacent pins. In doing so, the two inner most pins ( pins
the automatic device selection by the software. For further details, 15 and 16) will not have the feedback option as these pins are
refer to the compiler software manuals.
always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
Registered
Complex
Simple
Auto Mode Select
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
P16V8R
G16V8MS
GAL16V8_R
"Registered"1
P16V8R2
P16V8C
G16V8MA
GAL16V8_C7
"Complex"1
P16V8C2
P16V8AS
G16V8AS
GAL16V8_C8
"Simple"1
P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8
P16V8C2
G16V8R
G16V8C
G16V8AS3
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
3
LATTICE [ LATTICE SEMICONDUCTOR ]
