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GAL16V8D-7LR/833 参数 Datasheet PDF下载

GAL16V8D-7LR/833图片预览
型号: GAL16V8D-7LR/833
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 8 页 / 108 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16V8/883  
fmax Descriptions  
CLK  
LOGIC  
ARRAY  
REGISTER  
CLK  
LOGIC  
ARRAY  
t
su  
tco  
REGISTER  
fmax with External Feedback 1/(tsu+tco)  
Note: fmax with external feedback is calculated from measured  
tsu and tco.  
t
cf  
pd  
CLK  
t
fmax with Internal Feedback 1/(tsu+tcf)  
LOGIC  
REGISTER  
ARRAY  
Note: tcf is a calculated value, derived by subtracting tsu from  
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The  
value of tcf is used primarily when calculating the delay from  
clocking a register to a combinatorial output (through registered  
feedback), as shown above. For example, the timing from clock  
to a combinatorial output is equal to tcf + tpd.  
t
su + th  
fmax with No Feedback  
Note: fmax with no feedback may be less than 1/(twh + twl). This  
is to allow for a clock duty cycle of other than 50%.  
Switching Test Conditions  
+5V  
Input Pulse Levels  
GND to 3.0V  
3ns 10% 90%  
1.5V  
Input Rise and Fall Times  
Input Timing Reference Levels  
Output Timing Reference Levels  
R
1
1.5V  
Output Load  
See Figure  
3-state levels are measured 0.5V from steady-state active level.  
FROM OUTPUT (O/Q)  
UNDER TEST  
TEST POINT  
Output Load Conditions (see figure)  
C L*  
Test Condition  
R1  
R2  
CL  
R
2
A
B
390Ω  
390Ω  
750Ω  
750Ω  
750Ω  
750Ω  
750Ω  
50pF  
50pF  
50pF  
5pF  
Active High  
Active Low  
Active High  
Active Low  
C
390Ω  
5pF  
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE  
7
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