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GAL16V8D-7LR/833 参数 Datasheet PDF下载

GAL16V8D-7LR/833图片预览
型号: GAL16V8D-7LR/833
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 8 页 / 108 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16V8D/883  
AC Switching Characteristics  
Over Recommended Operating Conditions  
-15  
-20  
-30  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Combinational Output  
Clock to Output Delay  
3
2
15  
12  
12  
3
2
20  
15  
15  
3
2
30  
20  
20  
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
12  
15  
25  
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
A
0
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
41.6  
33.3  
22.2  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
41.6  
50  
33.3  
41.6  
22.2  
33.3  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
10  
10  
12  
12  
15  
15  
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
OE to Output Enabled  
15  
15  
20  
18  
30  
25  
ns  
ns  
tdis  
C
C
Input or I/O to Output Disabled  
OE to Output Disabled  
15  
15  
20  
18  
30  
25  
ns  
ns  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
10  
10  
CI/O  
pF  
*Characterized but not 100% tested.  
5
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