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GAL16V8D-20LD/833 参数 Datasheet PDF下载

GAL16V8D-20LD/833图片预览
型号: GAL16V8D-20LD/833
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 8 页 / 108 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL16V8D-7/10/883
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
TEST
COND
1
.
A
A
A
DESCRIPTION
Input or I/O to Combinational Output
Clock to Output Delay
Clock to Feedback Delay
Setup Time, Input or Feedback before Clock↑
Hold Time, Input or Feedback after Clock↑
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
Input or I/O to Output Enabled
OE to Output Enabled
Input or I/O to Output Disabled
OE to Output Disabled
1
1
7
0
76.9
-7
MIN. MAX.
7.5
6
6
-10
MIN. MAX.
2
1
10
0
58.8
10
7
7
UNITS
ns
ns
ns
ns
ns
MHz
t
pd
t
co
t
cf
2
t
su
t
h
f
max
3
A
A
76.9
100
58.8
62.5
MHz
MHz
t
wh
t
wl
t
en
t
dis
B
B
C
C
5
5
1
1
1
1
9
7
9
7
8
8
10
10
10
10
ns
ns
ns
ns
ns
ns
1) Refer to
Switching Test Conditions
section.
2) Calculated from
fmax
with internal feedback. Refer to
fmax Descriptions
section.
3) Refer to
fmax Descriptions
section.
Capacitance (T
A
= 25°C, f = 1.0 MHz)
SYMBOL
C
I
C
I/O
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
10
10
UNITS
pF
pF
TEST CONDITIONS
V
CC
= 5.0V, V
I
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
3