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GAL16LV8C-7LJN 参数 Datasheet PDF下载

GAL16LV8C-7LJN图片预览
型号: GAL16LV8C-7LJN
PDF下载: 下载PDF文件 查看货源
内容描述: 低压E2CMOS PLD通用阵列Logic⑩ [Low Voltage E2CMOS PLD Generic Array Logic⑩]
分类和应用:
文件页数/大小: 22 页 / 282 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16LV8C  
AC Switching Characteristics  
Over Recommended Operating Conditions (Unless Otherwise Specified)  
COM  
COM  
COM  
-15  
-7  
-10  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX.  
MIN. MAX.  
MIN. MAX.  
tpd2  
tco2  
tcf3  
tsu  
th  
A
A
Input or I/O to Combinational Output  
Clock to Output Delay  
1
1
7.5  
5
1
1
10  
7
1
1
15  
10  
8
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
6
4
7
5
12  
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
A
0
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
90.9  
71.4  
45.5  
MHz  
fmax4  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
100  
100  
83.3  
83.3  
50  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
62.5  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
5
5
6
6
8
8
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
OE to Output Enabled  
9
6
10  
8
15  
15  
ns  
ns  
tdis  
C
C
Input or I/O to Output Disabled  
OE to Output Disabled  
9
6
10  
8
15  
15  
ns  
ns  
1) Refer to Switching Test Conditions section.  
2) Minimum values for tpd and tco are not 100% tested but established by characterization.  
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
4) Refer to fmax Descriptions section. Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
TYPICAL  
UNITS  
pF  
TEST CONDITIONS  
VCC = 3.3V, VI = 0V  
VCC = 3.3V, VI/O = 0V  
CI  
8
8
CI/O  
pF  
13