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GAL16LV8C-7LJN 参数 Datasheet PDF下载

GAL16LV8C-7LJN图片预览
型号: GAL16LV8C-7LJN
PDF下载: 下载PDF文件 查看货源
内容描述: 低压E2CMOS PLD通用阵列Logic⑩ [Low Voltage E2CMOS PLD Generic Array Logic⑩]
分类和应用:
文件页数/大小: 22 页 / 282 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16LV8D  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-3  
COM  
-5  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX.  
MIN. MAX.  
tpd2  
tco2  
tcf3  
tsu  
th  
A
A
Input or I/O to Combinational Output  
Clock to Output Delay  
1
1
3.5  
2.5  
2
1
1
5
3
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
3
4
2
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
A
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
180  
142.8  
MHz  
fmax4  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
200  
250  
166  
166  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh4  
twl4  
ten  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
2
2
3
3
ns  
ns  
B
B
Input or I/O to Output Enabled  
OE to Output Enabled  
4.5  
3.5  
6
5
ns  
ns  
tdis  
C
C
Input or I/O to Output Disabled  
OE to Output Disabled  
4.5  
3.5  
6
5
ns  
ns  
1) Refer to Switching Test Conditions section.  
2) Minimum values for tpd and tco are not 100% tested but established by characterization.  
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
4) Refer to fmax Descriptions section. Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
TYPICAL  
UNITS  
pF  
TEST CONDITIONS  
VCC = 3.3V, VI = 0V  
VCC = 3.3V, VI/O = 0V  
CI  
5
5
CI/O  
pF  
11