Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-36. DQS Local Bus
PIO
Output
Register Block
DDR
Datain
PAD
DQSXFER
sysIO
Buffer
Input
Register Block
DI
GSR
CEI
To Sync
Reg.
CLK1
DQS
DQS
To DDR
Reg.
DQS
Strobe
PAD
sysIO
Buffer
PIO
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration bus
from DLL
DCNTL[6:0]
ECLK1
DQSXFER
DQSXFERDEL*
DCNTL[6:0]
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
Polarity Control Logic
In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown.
The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up
and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector
is used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-
amble state. This signal is used to control the polarity of the clock to the synchronizing registers.
2-39
LATTICE [ LATTICE SEMICONDUCTOR ]
