Lattice Semiconductor
Figure 2-4. Slice Diagram
FCO To Different Slice/PFU
Architecture
LatticeECP2/M Family Data Sheet
SLICE
FXB
FXA
A1
B1
C1
D1
CO
LUT4 &
CARRY*
CI
OFX1
F/SUM
D
FF*
To
Routing
LUT5
Mux
F1
Q1
M1
M0
From
Routing
OFX0
A0
B0
C0
D0
CO
LUT4 &
CARRY*
CI
F0
F/SUM
D
FF*
Q0
CE
CLK
LSR
*
Not
in Slice 3
FCI From Different Slice/PFU
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
Table 2-2. Slice Signal Descriptions
Function
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Type
Data signal
Data signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Inter-slice signal
Inter-slice signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
Signal Names
A0, B0, C0, D0
A1, B1, C1, D1
M0
M1
CE
LSR
CLK
FC
FXA
FXB
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-in
1
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
2
MUX depending on the slice
Slice 2 of each PFU is the fast carry chain output
1
Description
1. See Figure 2-4 for connection details.
2. Requires two PFUs.
2-4
LATTICE [ LATTICE SEMICONDUCTOR ]
