DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
sysCLOCK GPLL Timing
Over Recommended Operating Conditions
Parameter
Description
Conditions
Without external capacitor
With external capacitor5, 6
Without external capacitor
With external capacitor5
Without external capacitor
With external capacitor5
Min.
20
Typ.
—
—
—
—
—
—
—
—
—
Max.
420
420
420
50
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f
f
Input Clock Frequency (CLKI, CLKFB)
IN
2
20
Output Clock Frequency (CLKOP,
CLKOS)
OUT
5
0.156
0.039
640
20
210
25
f
f
f
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
OUT2
VCO
PFD
1280
420
50
Without external capacitor
With external capacitor5, 6
Phase Detector Input Frequency
2
AC Characteristics
t
t
Output Clock Duty Cycle
Default duty cycle selected3
45
—
50
—
—
55
0.05
125
0.025
0.04
250
—
%
UI
DT
PH
4
Output Phase Accuracy
Output Clock Period Jitter
f
≥ 100 MHz
—
ps
OUT
1
t
50 ≤ f
< 100 MHz
—
UIPP
UIPP
ps
OPJIT
OUT
f
< 50 MHz
—
—
—
—
—
—
130
—
—
—
—
—
—
—
OUT
t
t
Input Clock to Output Clock Skew
N/M = integer
—
SK
Output Clock Pulse Width
At 90% or 10%
1
ns
W
Without external capacitor
With external capacitor5
—
150
500
360
200
10
µs
2
t
PLL Lock-in Time
LOCK
—
µs
t
t
t
t
t
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
85
—
ps
PA
ps
IPJIT
—
ns
FBKDLY
HI
90% to 90%
10% to 10%
0.5
0.5
15
500
20
—
ns
Input Clock Low Time
—
ns
LO
RST Pulse Width (RESETM/RESETK)
—
ns
t
Without external capacitor
With external capacitor5
—
ns
RST
Reset Signal Pulse Width (CNTRST)
—
µs
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after t for PLL reset and dynamic delay adjustment.
LOCK
3. Using LVDS output buffers.
4. Relative to CLKOP.
5. Value of external capacitor: 5.6 nF 20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. f (max) = f * 10 for f < 5MHz.
OUT
IN
IN
Timing v.A 0.11
3-35