DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type
LVCMOS25_4mA
LVCMOS25_8mA
LVCMOS25_12mA
LVCMOS25_16mA
LVCMOS25_20mA
LVCMOS18_4mA
LVCMOS18_8mA
LVCMOS18_12mA
LVCMOS18_16mA
LVCMOS15_4mA
LVCMOS15_8mA
LVCMOS12_2mA
LVCMOS12_6mA
PCI33
Description
-7
-6
-5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS 2.5 4mA drive, slow slew rate
LVCMOS 2.5 8mA drive, slow slew rate
LVCMOS 2.5 12mA drive, slow slew rate
LVCMOS 2.5 16mA drive, slow slew rate
LVCMOS 2.5 20mA drive, slow slew rate
LVCMOS 1.8 4mA drive, slow slew rate
LVCMOS 1.8 8mA drive, slow slew rate
LVCMOS 1.8 12mA drive, slow slew rate
LVCMOS 1.8 16mA drive, slow slew rate
LVCMOS 1.5 4mA drive, slow slew rate
LVCMOS 1.5 8mA drive, slow slew rate
LVCMOS 1.2 2mA drive, slow slew rate
LVCMOS 1.2 6mA drive, slow slew rate
PCI33
2.18
2.19
1.50
1.60
1.43
2.22
1.93
1.43
1.47
2.32
1.84
2.52
1.69
0.04
2.26
2.35
1.66
1.59
1.39
2.27
2.08
1.51
1.46
2.38
1.98
2.63
1.83
0.04
2.33
2.51
1.82
1.58
1.34
2.32
2.23
1.58
1.45
2.43
2.12
2.74
1.96
0.04
1. Timing Adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. These timing adders are measured with the recommended resistor values.
Timing v.A 0.11
3-34
LATTICE [ LATTICE SEMICONDUCTOR ]
