DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
-7
-6
-5
Parameter
Description
Device
LFE2-6
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
Units
ns
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
—
—
—
ns
—
—
—
ns
—
—
—
ns
—
—
—
ns
Clock to Data Hold - PIO Input
Register with Input Data Delay
t
f
—
—
—
ns
H_DELE
—
—
—
ns
—
—
—
ns
—
—
—
ns
—
—
—
ns
—
—
—
ns
Clock Frequency of I/O and PFU
Register
ECP2/M
—
420
—
357
—
311
MHz
MAX_IOE
General I/O Pin Parameters (using Primary Clock with PLL)1
LFE2-6
—
—
2.30
2.30
2.30
2.30
2.30
2.30
2.30
2.30
2.60
2.60
2.70
—
—
—
2.60
2.60
2.60
2.60
2.60
2.60
2.60
2.60
2.90
2.90
3.00
—
—
—
2.80
2.80
2.80
2.80
2.80
2.80
2.80
2.80
3.10
3.10
3.20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LFE2-12
LFE2-20
LFE2-35
LFE2-50
—
—
—
—
—
—
—
—
—
Clock to Output - PIO Output
Register
10
t
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
LFE2-6
—
—
—
COPLL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
1.00
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
—
—
—
—
—
—
—
—
—
—
—
—
Clock to Data Setup - PIO Input
Register
t
—
—
—
SUPLL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-22
LATTICE [ LATTICE SEMICONDUCTOR ]
