DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
sysI/O Recommended Operating Conditions
V
V
(V)
REF
CCIO
Standard
LVCMOS 3.32
LVCMOS 2.52
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.22
LVTTL2
Min.
3.135
2.375
1.71
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.8
2.5
3.3
1.5
1.8
2.5
2.5
3.3
2.5
2.5
1.8
2.5
3.3
1.5
1.8
Max.
3.465
2.625
1.89
Min.
—
Typ.
—
Max.
—
—
—
—
—
—
—
1.425
1.14
1.575
1.26
—
—
—
—
—
—
3.135
3.135
1.71
3.465
3.465
1.89
—
—
—
PCI
—
—
—
SSTL182 Class I, II
SSTL22 Class I, II
SSTL32 Class I, II
HSTL2 15 Class I
HSTL2 18 Class I, II
LVDS2
MLVDS251
LVPECL331, 2
BLVDS251, 2
0.833
1.15
1.3
0.68
0.816
—
0.9
1.25
1.5
0.75
0.9
—
0.969
1.35
1.7
0.9
1.08
—
2.375
3.135
1.425
1.71
2.625
3.465
1.575
1.89
2.375
2.375
3.135
2.375
2.375
1.71
2.625
2.625
3.465
2.625
2.625
1.89
—
—
—
—
—
—
—
—
—
RSDS1, 2
—
—
—
SSTL18D_I2, II2
SSTL25D_ I2, II2
SSTL33D_ I2, II2
HSTL15D_ I2
HSTL18D_ I2, II2
—
—
—
2.375
3.135
1.425
1.71
2.625
3.465
1.575
1.89
—
—
—
—
—
—
—
—
—
—
—
—
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
2. Input on this standard does not depend on the value of V
.
CCIO
3-9
LATTICE [ LATTICE SEMICONDUCTOR ]
