Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA
LFE2-20E/20SE
LFE2-35E/35SE
Ball
Ball/Pad
Function
Ball/Pad
Function
Number
Bank
Dual Function
VREF2_7
Differential
T (LVDS)*
C (LVDS)*
Bank
7
7
-
Dual Function
Differential
T (LVDS)*
C (LVDS)*
D2
D1
PL2A
PL2B
GNDIO7
PL3A
PL3B
VCCIO7
NC
7
7
-
PL2A
PL2B
VREF2_7/LDQ6
VREF1_7/LDQ6
VREF1_7
GND
F6
GNDIO7
PL3A
7
7
7
-
T
7
7
7
7
7
7
7
-
LDQ6
LDQ6
T
F5
C
PL3B
C
VCCIO
E4
VCCIO7
PL4A
LDQ6
LDQ6
LDQ6
LDQ6
T (LVDS)*
E3
NC
-
PL4B
C (LVDS)*
E2
NC
-
PL5A
T
E1
NC
-
PL5B
C
GND
H6
GNDIO7
NC
-
GNDIO7
PL6A
-
7
7
7
7
7
7
7
7
-
LDQS6
LDQ6
LDQ6
T (LVDS)*
C (LVDS)*
T
H5
NC
-
PL6B
F2
NC
-
PL7A
VCCIO
F1
VCCIO7
NC
7
-
VCCIO7
PL7B
LDQ6
LDQ6
LDQ6
LDQ6
C
H8
NC
-
PL8A
T (LVDS)*
C (LVDS)*
T
J9
NC
-
PL8B
G4
NC
-
PL9A
GND
G3
GNDIO7
NC
-
GNDIO7
PL9B
-
7
7
7
7
7
7
7
7
7
7
7
-
LDQ6
LDQ14
LDQ14
LDQ14
LDQ14
LDQ14
C
H7
PL4A
PL4B
PL5A
PL5B
PL6A
VCCIO7
PL6B
PL7A
PL7B
PL8A
GNDIO7
PL8B
PL9A
PL9B
VCCIO7
PL10A
PL10B
PL11A
PL11B
GNDIO7
VCCIO7
NC
7
7
7
7
7
7
7
7
7
7
-
LDQ8
LDQ8
LDQ8
LDQ8
LDQ8
T (LVDS)*
C (LVDS)*
T
PL10A
PL10B
PL11A
PL11B
PL12A
VCCIO7
PL12B
PL13A
PL13B
PL14A
GNDIO7
PL14B
PL15A
PL15B
VCCIO7
PL16A
PL16B
PL17A
PL17B
GNDIO7
VCCIO7
NC
T (LVDS)*
C (LVDS)*
T
J8
G2
G1
C
C
H3
T (LVDS)*
T (LVDS)*
VCCIO
H4
LDQ8
LDQ8
LDQ8
LDQS8
C (LVDS)*
LDQ14
LDQ14
LDQ14
LDQS14
C (LVDS)*
J5
T
C
T
C
J4
J3
T (LVDS)*
T (LVDS)*
GND
K4
7
7
7
7
7
7
7
7
-
LDQ8
LDQ8
LDQ8
C (LVDS)*
7
7
7
7
7
7
7
7
-
LDQ14
LDQ14
LDQ14
C (LVDS)*
H1
T
T
H2
C
C
VCCIO
K6
LDQ8
LDQ8
LDQ8
LDQ8
T (LVDS)*
LDQ14
LDQ14
LDQ14
LDQ14
T (LVDS)*
K7
C (LVDS)*
C (LVDS)*
J1
T
T
J2
C
C
GND
VCCIO
K3
7
-
7
-
K2
NC
-
NC
-
GND
K1
GNDIO7
NC
-
GNDIO7
NC
-
-
-
L2
NC
-
NC
-
4-73
LATTICE [ LATTICE SEMICONDUCTOR ]
