Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA
LFE2-35E/SE
LFE2-50E/SE
Ball
Number
Ball/Pad
Function
Ball/Pad
Function
Bank
Dual Function
Differential
Bank
Dual Function
Differential
N10
N11
N12
N13
N15
N8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCPLL
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
GND
GND
P14
P20
P3
GND
GND
GND
P9
GND
R10
R11
R12
R13
U17
U6
GND
GND
GND
GND
GND
GND
W2
W21
Y14
Y9
GND
GND
GND
GND
A1
GND
N18
K6
VCCPLL
VCCPLL
VCCPLL
VCCPLL
N6
VCCPLL
NC
J16
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-72
LATTICE [ LATTICE SEMICONDUCTOR ]
