Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)
LFE2-6E/SE
LFE2-12E/12SE
Pin
Number
Pin/Pad
Function
Pin/Pad
Function
Dual
Function
Bank
Dual Function
Differential
Bank
Differential
136
137
138
139
140
141
142
143
144
PT6B
PT6A
0
0
-
C
T
PT16B
PT16A
GND
0
0
-
C
T
GND
VCCIO0
PT4B
0
0
0
-
VCCIO0
PT6B
0
0
0
-
C
T
C
T
PT4A
PT6A
VCCAUX
PT2B
VCCAUX
PT2B
0
0
VREF2_0
VREF1_0
C
T
0
0
VREF2_0
VREF1_0
C
T
PT2A
PT2A
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one
connection with a package ball or pin.
4-25
LATTICE [ LATTICE SEMICONDUCTOR ]
