Specifications ispLSI 8840
Signal Descriptions
Signal Name
Description
CLK0, CLK1,
CLK2
Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock
inputs of all GLB registers in the device.
CLKEN
Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for
each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate
the clock to the register.
GIOCLK0,
GIOCLK1
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to one of the clock
inputs of all I/O registers in the device.
GND
Ground (GND)
GOE
Global Output Enable inputs.
SET/RESET
Dedicated reset/preset pin connected to ALL registers in the device, GLB registers and
I/O registers. Each register can independently choose to be reset or preset when this signal goes
active. The active polarity is user-selectable.
IOCLKEN
Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for
all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the
clock to the I/O register.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
BSCAN/ispEN
Input – Dedicated in-system programming enable input. When this is high, the BSCAN TAP
controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State
Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the
device in the Lattice ISP programming mode and put all I/O in the high-Z state.
TMS/MODE
NC1
Input – This signal performs two functions. It is the Test Mode Select input signal when ispEN is logic
high. When ispEN is logic low, it controls the operation of the ISP State Machine.
No connect.
QIOCLK0
QIOCLK1
QIOCLK2
QIOCLK3
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers
on the same side of the device only, they are not connected to all of the I/O registers. Use of these
quadrant I/O clocks gives the fastest tco from the device.
TCK/SCLK
Input – This signal performs two functions. It is the Test Clock input signal when ispEN is logic high.
When ispEN is logic low, it functions as a clock signal for the Serial Shift Register.
TDI/SDI
Input – This signal performs two functions. It is the Test Data input signal when ispEN is logic high.
When ispEN is logic low, it functions as an input to load programming data into the device. SDI is also
used as one of the two control signals for the ISP State Machine.
TDO/SDO
Output – This signal performs two functions. When ispEN is logic low, it reads the ISP data. When
ispEN is high, it functions as Test Data Out.
TOE
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
VCC
Vcc
VCCIO
Power supply for the output drivers. The internal logic of the device is connected to VCC which is
always 5V. The output drivers are connected to VCCIO which can be equal to VCC or 3.3V. This allows
the output drivers to be powered from 3.3V, for example, to interface directly with another 3.3V device.
1. NC pins are not to be connected to any active signals, VCC or GND.
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LATTICE [ LATTICE SEMICONDUCTOR ]
