Specifications ispLSI 8840
Internal Timing Parameters
Over Recommended Operating Conditions
-110
MAX
-90
-60
PARA-
METER
2
#
DESCRIPTION
MIN
MIN
MAX
MIN
MAX UNITS
I/O Cell Delay
tidcom 23 Input Pad and Input Buffer, Combinatorial Input
–
–
0.1
8.0
0.0
0.2
2.0
1.0
–
–
–
0.1
9.4
0.0
0.2
2.4
1.2
–
–
–
0.2
13.9
0.0
0.4
3.6
2.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tidreg
tobp
tibp
tiolat
tioco
tiosu
tioh
24 Input Pad and Input Buffer, Registered Input
25 Output Register/Latch Bypass to Output Buffer
26 Input Register/Latch Bypass to BFM Routing or GRP
27 I/O Cell Latch, Transparent Mode
–
–
–
–
–
–
–
–
–
28 I/O Cell Register/Latch, Clk/Gate to Output
29 I/O Cell Register/Latch, Setup Time
–
–
–
0.4
4.1
–
0.7
4.4
–
1.4
6.9
–
30 I/O Cell Register/Latch, Hold Time
–
–
–
tiorst
31 I/O Cell Register/Latch, Reset or Set Time
2.3
–
2.9
–
4.4
–
tiosuce 32 I/O Cell Register/Latch, Setup Time for Clk Enable
tiohce 33 I/O cell Register/Latch, Hold Time for Clk Enable
todreg 34 I/O Cell Output Buffer Delay, Registered Output
todcom 35 I/O Cell Output Buffer Delay, Combinatorial Output
2.6
1.9
–
2.7
1.9
–
3.8
2.9
–
–
–
–
1.1
1.7
2.0
0.0
5.0
1.3
2.0
2.3
0.0
5.0
1.9
3.0
3.5
0.0
7.5
–
–
–
todz
tslf
tsls
36 Output Driver Disable Time
–
–
–
37 Slew Rate Adder, Fast Slew Rate
38 Slew Rate Adder, Slow Slew Rate
–
–
–
–
–
–
GLB / Macrocell Delay
tandhs 39 AND Array, High Speed Mode
–
–
3.6
7.1
3.6
0.2
3.4
3.7
0.0
0.2
0.2
–
–
–
4.2
8.4
4.3
0.3
4.4
4.5
0.0
0.3
0.3
–
–
–
6.4
12.6
6.2
0.4
6.1
6.8
0.0
0.9
0.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tandlp
t1pt
40 AND Array, Low Power Mode
41 Single Product Term Bypass
–
–
–
t4ptcom 42 Four Product Term Bypass, Combinatorial Macrocell
t4ptreg 43 Four Product Term Bypass, Registered Macrocell
–
–
–
–
–
–
tptsa
tmbp
tmlat
tmco
tmsu
tmh
44 Product Term Sharing Array
–
–
–
45 Macrocell Register/Latch Bypass
–
–
–
46 Macrocell Latch, Transparent Mode
47 Macrocell Register/Latch, Clk/Gate to Output
48 Macrocell Register/Latch, Setup Time
49 Macrocell Register/Latch, Hold Time
50 Macrocell Register/Latch, Reset or Set Time
–
–
–
–
–
–
0.4
3.8
–
0.8
4.5
–
1.2
6.1
–
–
–
–
tmrst
4.0
–
5.2
–
7.3
–
tmsuce 51 Macrocell Register/Latch, Setup Time for Clk Enable 1.7
1.8
0.9
–
2.4
1.3
–
tmhce
tftog
tfloc
52 Macrocell Register/Latch, Hold Time for Clk Enable
1.0
–
–
–
53 Toggle Flip-Flop Feedback
–
3.9
1.1
2.5
2.6
2.4
2.4
1.7
1.8
4.7
1.3
3.5
3.1
2.5
2.5
2.0
2.1
6.8
1.9
5.3
4.6
3.8
3.8
3.0
2.7
54 Local Feedback to AND Array
55 Single Product Term, Clk
–
–
–
tpck
1.0
–
1.5
–
2.3
–
tpcken 56 Single Product Term, Clk Enable
tsck 57 Shared Product Term, Clk
tscken 58 Shared Product Term, Clk Enable
1.6
–
1.8
–
2.7
–
tprst
trdir
59 Single Product Term, Reset or Set Delay
–
–
–
60 Macrocell Register, Direct Input from GRP
–
–
–
14
LATTICE [ LATTICE SEMICONDUCTOR ]
