Specifications ispGDX240VA
Switching Waveforms
DATA
VALID INPUT
MUXSEL (I/O INPUT)
VALID INPUT
(I/O INPUT)
h
t
t
su
tsel
t
gco
DATA (I/O INPUT)
VALID INPUT
CLK
t
co
tpd
COMBINATORIAL
I/O OUTPUT
REGISTERED
I/O OUTPUT
1/
fmax
Combinatorial Output
(external fdbk)
t
suce
t
ceh
OE (I/O INPUT)
CLKEN
RESET
dis
en
t
t
Registered Output
COMBINATORIAL
I/O OUTPUT
I/O Output Enable/Disable
trw
trst
wh
t
wl
t
REGISTERED
I/O OUTPUT
CLK
(I/O INPUT)
Clock Width
Reset
ispGDXVA Timing Model
tgoe #58
OE
tmuxd #34
tmuxs #36
tmuxio #37
tmuxg #38
tmuxcg #50
tmuxcio #51
MUX Expander Output
tmuxexp #35
tmuxselexp #39
MUX Expander Input
TOE
ttoe #59
A
B
C
D
tiobp #48
D
Q
tioob #49
MUX0
I/O Pin
CLKEN
CLK
MUX1
GRP
tob #54
tobs #55
toeen #56
toedis #57
tiolat #40
tiosu #41
tioh #42
tioco #43
tior #44
tcesu #45
tceh #46
tgrp #33
tiod #52, #53
tio #32
RESET
tgr #65
tfdbk #47
CLKEN
tioclkeg #64
tioclk #60
CLK
Y0,1,2,3
0902/gdx160v/va
tgclk #61
Y0,1,2,3, Enable
tgclkeng #62
tgclkenio #63
14
LATTICE [ LATTICE SEMICONDUCTOR ]
