Specifications
ispLSI 1048C/883
ispLSI 1048C/883 Timing Model
I/O Cell
GRP
Feedback
Ded. In
GLB
ORP
I/O Cell
#30
I/O Reg Bypass
#24
Input
D Register Q
RST
#25 - 29
GRP 4
#32
GRP
Loading
Delay
#31, 33,
34, 35
4 PT Bypass
#36
20 PT
XOR Delays
#37, 38, 39
#59
D
RST
#41,
42,
43, 44
GLB Reg Bypass
#40
GLB Reg
Delay
Q
ORP Bypass
#49
ORP
Delay
#48
#50
I/O Pin
(Output)
#51, 52
I/O Pin
(Input)
#59
Reset
Clock
Distribution
Y1,2,3
#55, 56,
57, 58
#54
#53
Control RE
PTs
OE
#45, 46, CK
47
Y0
GOE0, 1
0491A/48
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#24 + #32 + #47
)
8.0 ns = (4.3 + 6.7 + 7.5) + (3.9) - (4.3 + 6.7 + 3.4)
= Clock (max) + Reg h - Logic
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#24 + #32 + #47
)
+
(
#42
) - (
#24 + #32 + #38
)
8.0 ns = (4.3 + 6.7 + 8.2) + (7.3) - (4.3 + 6.7 + 7.5)
t
h
t
co
= Clock (max) + Reg co + Output
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#24 + #32 + #47
)
+
(
#43
)
+
(
#48 + #50
)
32.8 ns = (4.3 + 6.7 + 8.2) + (7.3) + (3.4 + 2.9)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#54 + #43 + #56
)
10.1 ns= (4.3 + 6.7 + 7.5) + (3.9) - (7.4 + 2.3 + 2.6)
t
h
= Clock (max) + Reg h - Logic
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#54 + #43 + #56
)
+
(
#42
) - (
#24 + #32 + #38
)
6.1 ns = (7.4 + 2.3 + 7.6) + (7.3) - (4.3 + 6.7 + 7.5)
t
co
= Clock (max) + Reg co + Output
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#54 + #43 + #56
)
+
(
#43
)
+
(
#48 + #50
)
30.9 ns = (7.4 + 2.3 + 7.6) + (7.3) + (3.4 + 2.9)
1. Calculations are based upon timing specifications for the ispLSI 1048C-50
8
LATTICE [ LATTICE SEMICONDUCTOR ]
