Specifications
ispLSI 1048C/883
Internal Timing Parameters
1
2
PARAMETER
#
DESCRIPTION
-50
MIN. MAX.
UNITS
Outputs
50
t
ob
51
t
oen
t
odis
52
t
goe
53
Clocks
t
gy0
54
t
gy1/2
55
t
gcp
56
t
ioy2/3
57
t
iocp
58
Global Reset
t
gr
59
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Global OE
–
–
–
–
2.9
6.9
6.9
13.6
ns
ns
ns
ns
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
7.4
6.1
2.6
6.1
2.6
7.4
8.7
7.6
8.7
7.6
ns
ns
ns
ns
ns
Global Reset to GLB and I/O Registers
–
11.4
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2- 0037-48C/50mil
7
LATTICE [ LATTICE SEMICONDUCTOR ]
