Specifications ispLSI and pLSI 1032
Pin Description
Name
CPGA Pin Numbers
Description
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
F1,
K1, J2,
K3, L2,
L4,
L7,
K8, L9,
L11, K10, J10, K11,
J11, H10, H11, F10,
E9, D11, D10, C11,
B11, C10, A11, B10,
B9, A10, A9, B8,
A8, B6,
A5, B5,
B4, A3,
A1, B2,
H1, H2, J1,
L1,
L3,
K2,
K4,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
J5,
K7,
K5, L5,
L6, L8,
L10, K9,
B7, A7,
C5, A4,
A2, B3,
C2, B1,
C1, D2, D1, E3
Dedicated input pins to the device.
IN 4 - IN 7
ispEN*/NC
E10, C7, A6, E2
G3
G2
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
SDI*/IN 0
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
MODE*/IN 1
SDO*/IN 2
SCLK*/IN 3
K6
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
J7
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
G10
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
RESET
Y0
G1
E1
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y1
E11
Y2
G9
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y3
G11
G3
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
NC
GND
This pin should be left floating or tied to VCC.
This pin should never be tied to GND.
C6, F3,
F2, F11
F9,
J6
Ground (GND)
VCC
V
CC
Table 2-0002-32/883
14
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
