Specifications ispLSI and pLSI 1032
Pin Description
Name
Description
TQFP Pin Numbers
I/O 0 - I/O 3
I/O 4 - I/O 7
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
7,
8,
9
Dedicated input pins to the device.
IN 4 - IN 7
ispEN*/NC
66,
14
87,
89,
10
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
SDI*/IN 0
16
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
MODE*/IN 1
SDO*/IN 2
SCLK*/IN 3
NC
37
39
60
1,
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
These pins are not used.
2,
24,
25,
26,
51,
76,
27,
52,
77,
49,
74,
99,
50,
75
100
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
RESET
Y0
15
11
65
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y2
62
61
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Y3
GND
13,
12,
38,
64
63,
88
Ground (GND)
VCC
V
CC
Table 2- 0002B-32-isp
* For ispLSI 1032 Only
13
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
