06 | Keysight | U4164A Logic Analyzer Module - Data Sheet
Product Description (Continued)
Figure 1D. DDR4 3300 Mb/s state waveform.
Figure 1E. DDR4 3300 Mb/s state waveform.
There are two methods to capture DDR or LPDDR memory DQ (data) transactions over
2500 Mb/s using the U4164A logic analyzer system:
1. Using quad-sample state mode, the U4164A is sampled on one clock edge, a single
probe load is placed on each DQ, and quad-sample mode is used to provide separate
read rising, read falling, write rising, and write falling edge captures with sample
positions set independently. Read and write thresholds can be set independently. Read
rising, read falling, write rising, and write falling edge captures are given different labels
in the configuration so that the sample positions can be set independently.
2. Using dual-sample state mode, the U4164A is sampled on one clock edge, double
probing of each DQ must be performed and provide separate read DQ and write DQ
samples, and dual-sample mode is used to provide a rising and falling edge sample for
each DQ, resulting in four samples taken for each DQ signal from two probe loads. Read
rising, read falling, write rising, and write falling edge captures are given different labels
so the sample positions can be set independently.
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