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N1092D 参数 Datasheet PDF下载

N1092D图片预览
型号: N1092D
PDF下载: 下载PDF文件 查看货源
内容描述: [N1090A, N1092A/B/C/D/E and N1094A/B DCA-M Optical and Electrical Sampling Oscilloscopes]
分类和应用:
文件页数/大小: 20 页 / 1439 K
品牌: KEYSIGHT [ Keysight Technologies ]
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15 | Keysight | N1090A, N1092A/B/C/D/E and N1094A/B DCA-M Optical and Electrical Sampling Oscilloscopes - Data Sheet  
N1092/4 Electrical Channel Specifications  
Electrical input channels  
Input connectors  
2.4 mm (m) bulkhead  
Bandwidth, 3 dB (user selectable)  
Transition time (10 to 90% calculated from TR = 0.35/BW)  
20, 33, 40, and 50 1 GHz (characteristic)  
20 GHz bandwidth  
17.5 ps (calculated)  
33 GHz bandwidth  
10.6 ps (calculated)  
8.8 ps (calculated)  
7.0 ps (calculated)  
40 GHz bandwidth 1  
50 GHz bandwidth 1  
Channel-to-channel skew range  
± 100 ps  
RMS noise  
20 GHz bandwidth  
33 GHz bandwidth  
40 GHz bandwidth 1  
50 GHz bandwidth 1  
RMS noise (Maximum)  
Scale factor (per division)  
Minimum  
310 μV (characteristic)  
450 μV (characteristic)  
500 μV (characteristic)  
600 μV (characteristic)  
700 μV (50 GHz bandwidth setting)  
1 mV/division  
Maximum  
100 mV/division  
DC accuracy (VAVG measurement)  
20, 33, 40, 50 GHz  
20, 33, 40, 50 GHz  
ADC resolution  
± 1.15 mV (characteristic)  
± 2 mV ± 4% of (reading – channel offset)  
16 bits  
DC offset range  
Referenced to center of screen  
Input dynamic range  
Relative to channel offset  
Maximum input signal  
± 500 mV  
± 400 mV  
± 2V (+16 dBm)  
50 Ω (characteristic)  
20% (characteristic)  
Nominal input impedance  
Reflections (for 30 ps rise time)  
1. 40 and 50 GHz performance is only available with N1094 Option 050 and N1092C/E.  
N1092/4 Clock Trigger Input Specifications  
Item  
Description  
0.5 to 28.5 GHz  
200 mVpp  
2.6 Vp-p  
50 Ω  
Clock input bandwidth 1  
Clock input sensitivity  
Maximal input signal  
Nominal impedance (AC coupled)  
Clock input connector  
2.92 mm (female)  
1. Minimum clock input frequency can be reduced to 100 MHz when it is a sub-rate clock of a channel input  
data rate in excess of 500 Mb/s and the clock divide ratio is a power of 2 (e.g. 2, 4, 8, 16...).  
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